Design and layout strategies for integrated frequency synthesizers with high spectral purity

Dieser Beitrag ist mit Zustimmung des Rechteinhabers aufgrund einer (DFG geförderten) Allianz- bzw. Nationallizenz frei zugänglich.This publication is with permission of the rights owner freely accessible due to an Alliance licence and a national licence (funded by the DFG, German Research Foundation) respectively.Design guidelines for fractional-N phase-locked loops with a high spectral purity of the output signal are presented. Various causes for phase noise and spurious tones (spurs) in integer-N and fractional-N phase-locked loops (PLLs) are briefly described. These mechanisms include device noise, quantization noise folding, and noise coupling from charge pump (CP) and reference input buffer to the voltage-controlled oscillator (VCO) and vice versa through substrate and bondwires. Remedies are derived to mitigate the problems by using proper PLL parameters and a careful chip layout. They include a large CP current, sufficiently large transistors in the reference input buffer, linearization of the phase detector, a high speed of the programmable frequency divider, and minimization of the cross-coupling between the VCO and the other building blocks. Examples are given based on experimental PLLs in SiGe BiCMOS technologies for space communication and wireless base stations.BMBF, 03ZZ0512A, Zwanzig20 - Verbundvorhaben: fast-spot; TP1: Modularer Basisband- Prozessor mit extrem hohen Datenraten, sehr kurzen Latenzzeiten und SiGe-Analog-Frontend-IC-Fertigung bei >200 GHz Trägerfrequen

SISSI-LO : Schlussbericht ; Berichtszeitraum: 01.07.2011 bis 31.10.2012

[no abstract available

System-level simulation of a noisy phase-locked loop

This paper presents a compact model of a noisy phase-locked loop (PLL) for inclusion in a time-domain system simulation. The phase noise of the reference is modeled as a Wiener process, and the phase noise contribution of the voltage-controlled oscillator (VCO) is described as an Ornstein-Uhlenbeck process. The model is applied to phase error modeling for a 60 GHz OFDM system including correction of the common phase error. A close agreement is observed between the time-domain simulation and a frequency-domain model

System-Level Simulation of a Noisy

Abstract — This paper presents a compact model of a noisy phase-locked loop (PLL) for inclusion in a timedomain system simulation. The phase noise of the reference is modeled as a Wiener process, and the phase noise contribution of the voltage-controlled oscillator (VCO) is described as an Ornstein-Uhlenbeck process. The model is applied to phase error modeling for a 60 GHz OFDM system including correction of the common phase error. A close agreement is observed between the time-domain simulation and a frequency-domain model. I